The present invention relates to clock circuits, and more specifically, to clock circuits for arrays.
High performance circuits, such as static random access memory (SRAM) arrays, usually require clock generation circuits to control internal circuit timings. These array local clock generators (also known as Local Clock Buffers, or LCBs) usually are used to control array word decode/bit decode and read/write critical circuit functionality. To provide timing tuning flexibilities as well as hardware debug capabilities, state of the art array LCBs often have programmable controls on their clock delay or pulse width circuits. Multiple discrete timing settings of delay or pulse width are implemented with explicit decoders and with typical inverter delay chains. Such programmability of timing settings of delay or pulse width however adds circuit complexity, chip area and power consumption to the LCB structures. A state of the art local clock control buffer is constructed with modular circuit blocks. This modular topology makes the design extremely flexible to drive different clock loads and latch types.
However, due to the constraints of timing programmability, the ability to shift and delay the launching clock of LCB is limited. For array control designs pulsed clocks are typically needed. Since the pulsed clocks are not changing with frequency, several programmable settings are required to allow for pulse width modulation (PWM) for timing adjustments and for debugging.